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<h1>Analog to Digital Convertor Peripheral</h1>
<null><a name="ADC"></a><b>ADC</b> <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_ADC">AT91S_ADC</a>)</font></i><b>  0xFFFD8000 </b><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_BASE_ADC">AT91C_BASE_ADC</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>4</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_ID_ADC">AT91C_ID_ADC</a>)</font></i></font></td><td><font size="-1">Analog-to-Digital Converter</font></td></tr>
</null></table><br><table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>ADTRG</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA8_ADTRG   ">AT91C_PA8_ADTRG   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: B Bit: 8</font></td><td><font size="-1">ADC External Trigger</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_CfgPMC">AT91F_ADC_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for ADC</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_CfgPIO">AT91F_ADC_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive ADC signals</font></td></tr>
</null></table><br><br></null><a name="ADC"></a><h2>ADC Software API <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_ADC">AT91S_ADC</a>)</font></i></h2>
<a name="ADC"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CR">ADC_CR</a></font></td><td><font size="-1">ADC Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_MR">ADC_MR</a></font></td><td><font size="-1">ADC Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1">ADC_CHER (<a href="#	ADC_CHER">	ADC_CHER</a>)</font></td><td><font size="-1">ADC Channel Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1">ADC_CHDR (<a href="#	ADC_CHDR">	ADC_CHDR</a>)</font></td><td><font size="-1">ADC Channel Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x18</b></font></td><td><font size="-1">ADC_CHSR (<a href="#	ADC_CHSR">	ADC_CHSR</a>)</font></td><td><font size="-1">ADC Channel Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x1C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_SR">ADC_SR</a></font></td><td><font size="-1">ADC Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x20</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_LCDR">ADC_LCDR</a></font></td><td><font size="-1">ADC Last Converted Data Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x24</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_IER">ADC_IER</a></font></td><td><font size="-1">ADC Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x28</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_IDR">ADC_IDR</a></font></td><td><font size="-1">ADC Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x2C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_IMR">ADC_IMR</a></font></td><td><font size="-1">ADC Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x30</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR0">ADC_CDR0</a></font></td><td><font size="-1">ADC Channel Data Register 0</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x34</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR1">ADC_CDR1</a></font></td><td><font size="-1">ADC Channel Data Register 1</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x38</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR2">ADC_CDR2</a></font></td><td><font size="-1">ADC Channel Data Register 2</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x3C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR3">ADC_CDR3</a></font></td><td><font size="-1">ADC Channel Data Register 3</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x40</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR4">ADC_CDR4</a></font></td><td><font size="-1">ADC Channel Data Register 4</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x44</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR5">ADC_CDR5</a></font></td><td><font size="-1">ADC Channel Data Register 5</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x48</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR6">ADC_CDR6</a></font></td><td><font size="-1">ADC Channel Data Register 6</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_ADC.html#ADC_CDR7">ADC_CDR7</a></font></td><td><font size="-1">ADC Channel Data Register 7</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x100</b></font></td><td><font size="-1">ADC_RPR (<a href="AT91SAM7S256_PDC.html#PDC_RPR">PDC_RPR</a>)</font></td><td><font size="-1">Receive Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x104</b></font></td><td><font size="-1">ADC_RCR (<a href="AT91SAM7S256_PDC.html#PDC_RCR">PDC_RCR</a>)</font></td><td><font size="-1">Receive Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x108</b></font></td><td><font size="-1">ADC_TPR (<a href="AT91SAM7S256_PDC.html#PDC_TPR">PDC_TPR</a>)</font></td><td><font size="-1">Transmit Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10C</b></font></td><td><font size="-1">ADC_TCR (<a href="AT91SAM7S256_PDC.html#PDC_TCR">PDC_TCR</a>)</font></td><td><font size="-1">Transmit Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x110</b></font></td><td><font size="-1">ADC_RNPR (<a href="AT91SAM7S256_PDC.html#PDC_RNPR">PDC_RNPR</a>)</font></td><td><font size="-1">Receive Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x114</b></font></td><td><font size="-1">ADC_RNCR (<a href="AT91SAM7S256_PDC.html#PDC_RNCR">PDC_RNCR</a>)</font></td><td><font size="-1">Receive Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x118</b></font></td><td><font size="-1">ADC_TNPR (<a href="AT91SAM7S256_PDC.html#PDC_TNPR">PDC_TNPR</a>)</font></td><td><font size="-1">Transmit Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x11C</b></font></td><td><font size="-1">ADC_TNCR (<a href="AT91SAM7S256_PDC.html#PDC_TNCR">PDC_TNCR</a>)</font></td><td><font size="-1">Transmit Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x120</b></font></td><td><font size="-1">ADC_PTCR (<a href="AT91SAM7S256_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x124</b></font></td><td><font size="-1">ADC_PTSR (<a href="AT91SAM7S256_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH0">AT91F_ADC_GetConvertedDataCH0</a></b></font></td><td><font size="-1">Return the Channel 0 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH1">AT91F_ADC_GetConvertedDataCH1</a></b></font></td><td><font size="-1">Return the Channel 1 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH2">AT91F_ADC_GetConvertedDataCH2</a></b></font></td><td><font size="-1">Return the Channel 2 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_CfgModeReg">AT91F_ADC_CfgModeReg</a></b></font></td><td><font size="-1">Configure the Mode Register of the ADC controller</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH3">AT91F_ADC_GetConvertedDataCH3</a></b></font></td><td><font size="-1">Return the Channel 3 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH4">AT91F_ADC_GetConvertedDataCH4</a></b></font></td><td><font size="-1">Return the Channel 4 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH5">AT91F_ADC_GetConvertedDataCH5</a></b></font></td><td><font size="-1">Return the Channel 5 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH6">AT91F_ADC_GetConvertedDataCH6</a></b></font></td><td><font size="-1">Return the Channel 6 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetConvertedDataCH7">AT91F_ADC_GetConvertedDataCH7</a></b></font></td><td><font size="-1">Return the Channel 7 Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetChannelStatus">AT91F_ADC_GetChannelStatus</a></b></font></td><td><font size="-1">Return ADC Timer Register Value</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetModeReg">AT91F_ADC_GetModeReg</a></b></font></td><td><font size="-1">Return the Mode Register of the ADC controller value</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_DisableIt">AT91F_ADC_DisableIt</a></b></font></td><td><font size="-1">Disable ADC interrupt</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_StartConversion">AT91F_ADC_StartConversion</a></b></font></td><td><font size="-1">Software request for a analog to digital conversion </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetStatus">AT91F_ADC_GetStatus</a></b></font></td><td><font size="-1">Return ADC Interrupt Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetLastConvertedData">AT91F_ADC_GetLastConvertedData</a></b></font></td><td><font size="-1">Return the Last Converted Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_SoftReset">AT91F_ADC_SoftReset</a></b></font></td><td><font size="-1">Software reset</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_CfgTimings">AT91F_ADC_CfgTimings</a></b></font></td><td><font size="-1">Configure the different necessary timings of the ADC controller</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_DisableChannel">AT91F_ADC_DisableChannel</a></b></font></td><td><font size="-1">Return ADC Timer Register Value</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_EnableIt">AT91F_ADC_EnableIt</a></b></font></td><td><font size="-1">Enable ADC interrupt</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_GetInterruptMaskStatus">AT91F_ADC_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return ADC Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_IsStatusSet">AT91F_ADC_IsStatusSet</a></b></font></td><td><font size="-1">Test if ADC Status is Set</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_EnableChannel">AT91F_ADC_EnableChannel</a></b></font></td><td><font size="-1">Return ADC Timer Register Value</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_ADC_IsInterruptMasked">AT91F_ADC_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if ADC Interrupt is Masked </font></td></tr>
</null></table></null><h2>ADC Register Description</h2>
<null><a name="ADC_CR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CR  <i>ADC Control Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CR">AT91C_ADC_CR</a></i> 0xFFFD8000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_SWRST"></a><b>ADC_SWRST</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_SWRST">AT91C_ADC_SWRST</a></font></td><td><b>Software Reset</b><br>0 = No effect.<br>1 = Resets the ADC simulating a hardware reset.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_START"></a><b>ADC_START</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_START">AT91C_ADC_START</a></font></td><td><b>Start Conversion</b><br>0 = No effect.<br>1 = Begins analog-to-digital conversion and clears all EOC bits.</td></tr>
</null></table>
<a name="ADC_MR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_MR  <i>ADC Mode Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_MR">AT91C_ADC_MR</a></i> 0xFFFD8004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_TRGEN"></a><b>ADC_TRGEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGEN">AT91C_ADC_TRGEN</a></font></td><td><b>Trigger Enable</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="ADC_TRGEN_DIS"></a><b>ADC_TRGEN_DIS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGEN_DIS">AT91C_ADC_TRGEN_DIS</a></font></td><td><br>Hradware triggers are disabled. Starting a conversion is only possible by software</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="ADC_TRGEN_EN"></a><b>ADC_TRGEN_EN</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGEN_EN">AT91C_ADC_TRGEN_EN</a></font></td><td><br>Hardware trigger selected by TRGSEL field is enabled.</td></tr>
</null></table></font>
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<tr><td align="CENTER" bgcolor="#FFFFCC">3..1</td><td align="CENTER"><a name="ADC_TRGSEL"></a><b>ADC_TRGSEL</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL">AT91C_ADC_TRGSEL</a></font></td><td><b>Trigger Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="ADC_TRGSEL_TIOA0"></a><b>ADC_TRGSEL_TIOA0</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL_TIOA0">AT91C_ADC_TRGSEL_TIOA0</a></font></td><td><br>Selected TRGSEL = TIAO0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="ADC_TRGSEL_TIOA1"></a><b>ADC_TRGSEL_TIOA1</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL_TIOA1">AT91C_ADC_TRGSEL_TIOA1</a></font></td><td><br>Selected TRGSEL = TIAO1</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="ADC_TRGSEL_TIOA2"></a><b>ADC_TRGSEL_TIOA2</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL_TIOA2">AT91C_ADC_TRGSEL_TIOA2</a></font></td><td><br>Selected TRGSEL = TIAO2</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="ADC_TRGSEL_TIOA3"></a><b>ADC_TRGSEL_TIOA3</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL_TIOA3">AT91C_ADC_TRGSEL_TIOA3</a></font></td><td><br>Selected TRGSEL = TIAO3</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="ADC_TRGSEL_TIOA4"></a><b>ADC_TRGSEL_TIOA4</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL_TIOA4">AT91C_ADC_TRGSEL_TIOA4</a></font></td><td><br>Selected TRGSEL = TIAO4</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="ADC_TRGSEL_TIOA5"></a><b>ADC_TRGSEL_TIOA5</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL_TIOA5">AT91C_ADC_TRGSEL_TIOA5</a></font></td><td><br>Selected TRGSEL = TIAO5</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="ADC_TRGSEL_EXT"></a><b>ADC_TRGSEL_EXT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_TRGSEL_EXT">AT91C_ADC_TRGSEL_EXT</a></font></td><td><br>Selected TRGSEL = External Trigger</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_LOWRES"></a><b>ADC_LOWRES</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_LOWRES">AT91C_ADC_LOWRES</a></font></td><td><b>Resolution.</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="ADC_LOWRES_10_BIT"></a><b>ADC_LOWRES_10_BIT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_LOWRES_10_BIT">AT91C_ADC_LOWRES_10_BIT</a></font></td><td><br>10-bit resolution</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="ADC_LOWRES_8_BIT"></a><b>ADC_LOWRES_8_BIT</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_LOWRES_8_BIT">AT91C_ADC_LOWRES_8_BIT</a></font></td><td><br>8-bit resolution</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_SLEEP"></a><b>ADC_SLEEP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_SLEEP">AT91C_ADC_SLEEP</a></font></td><td><b>Sleep Mode</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="ADC_SLEEP_NORMAL_MODE"></a><b>ADC_SLEEP_NORMAL_MODE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_SLEEP_NORMAL_MODE">AT91C_ADC_SLEEP_NORMAL_MODE</a></font></td><td><br>Normal Mode</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="ADC_SLEEP_MODE"></a><b>ADC_SLEEP_MODE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_SLEEP_MODE">AT91C_ADC_SLEEP_MODE</a></font></td><td><br>Sleep Mode</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="ADC_PRESCAL"></a><b>ADC_PRESCAL</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_PRESCAL">AT91C_ADC_PRESCAL</a></font></td><td><b>Prescaler rate selection</b><br>This field defines the conversion clock in function of the Master Clcok (MCK).<br>ADCClock = MCK/((PRESCAL + 1) x 2).<br> Range = MCK/2 to MCK/128.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">20..16</td><td align="CENTER"><a name="ADC_STARTUP"></a><b>ADC_STARTUP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_STARTUP">AT91C_ADC_STARTUP</a></font></td><td><b>Startup Time</b><br>This field defines the necessary startup time in function of the ADC Clock.<br>Startup Time = (STARTUP+1)* 8 / ADCClock.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">27..24</td><td align="CENTER"><a name="ADC_SHTIM"></a><b>ADC_SHTIM</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_SHTIM">AT91C_ADC_SHTIM</a></font></td><td><b>Sample &amp; Hold Time</b><br>This field defines the necessary time between 2 channels selection to guarantee the converted value in function of the ADC Clock.<br>Sample &amp; Hold Time = (SHTIM+1) / ADCClock.</td></tr>
</null></table>
<a name="ADC_CHER"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CHER  <i>ADC Channel Enable Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CHER">AT91C_ADC_CHER</a></i> 0xFFFD8010</font></null></ul><br>0 = No effect.<br> 1 = Enable the corresponding channel<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_CH0"></a><b>ADC_CH0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH0">AT91C_ADC_CH0</a></font></td><td><b>Channel 0</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_CH1"></a><b>ADC_CH1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH1">AT91C_ADC_CH1</a></font></td><td><b>Channel 1</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_CH2"></a><b>ADC_CH2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH2">AT91C_ADC_CH2</a></font></td><td><b>Channel 2</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_CH3"></a><b>ADC_CH3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH3">AT91C_ADC_CH3</a></font></td><td><b>Channel 3</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_CH4"></a><b>ADC_CH4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH4">AT91C_ADC_CH4</a></font></td><td><b>Channel 4</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_CH5"></a><b>ADC_CH5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH5">AT91C_ADC_CH5</a></font></td><td><b>Channel 5</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_CH6"></a><b>ADC_CH6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH6">AT91C_ADC_CH6</a></font></td><td><b>Channel 6</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_CH7"></a><b>ADC_CH7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH7">AT91C_ADC_CH7</a></font></td><td><b>Channel 7</b></td></tr>
</null></table>
<a name="ADC_CHDR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CHDR  <i>ADC Channel Disable Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CHDR">AT91C_ADC_CHDR</a></i> 0xFFFD8014</font></null></ul><br>0 = No effect.<br> 1 = Disable the corresponding channel<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_CH0"></a><b>ADC_CH0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH0">AT91C_ADC_CH0</a></font></td><td><b>Channel 0</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_CH1"></a><b>ADC_CH1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH1">AT91C_ADC_CH1</a></font></td><td><b>Channel 1</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_CH2"></a><b>ADC_CH2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH2">AT91C_ADC_CH2</a></font></td><td><b>Channel 2</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_CH3"></a><b>ADC_CH3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH3">AT91C_ADC_CH3</a></font></td><td><b>Channel 3</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_CH4"></a><b>ADC_CH4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH4">AT91C_ADC_CH4</a></font></td><td><b>Channel 4</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_CH5"></a><b>ADC_CH5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH5">AT91C_ADC_CH5</a></font></td><td><b>Channel 5</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_CH6"></a><b>ADC_CH6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH6">AT91C_ADC_CH6</a></font></td><td><b>Channel 6</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_CH7"></a><b>ADC_CH7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH7">AT91C_ADC_CH7</a></font></td><td><b>Channel 7</b></td></tr>
</null></table>
<a name="ADC_CHSR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CHSR  <i>ADC Channel Status Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CHSR">AT91C_ADC_CHSR</a></i> 0xFFFD8018</font></null></ul><br>0 = Corresponding channel is disabled.<br> 1 = Corresponding channel is enabled<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_CH0"></a><b>ADC_CH0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH0">AT91C_ADC_CH0</a></font></td><td><b>Channel 0</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_CH1"></a><b>ADC_CH1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH1">AT91C_ADC_CH1</a></font></td><td><b>Channel 1</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_CH2"></a><b>ADC_CH2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH2">AT91C_ADC_CH2</a></font></td><td><b>Channel 2</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_CH3"></a><b>ADC_CH3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH3">AT91C_ADC_CH3</a></font></td><td><b>Channel 3</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_CH4"></a><b>ADC_CH4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH4">AT91C_ADC_CH4</a></font></td><td><b>Channel 4</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_CH5"></a><b>ADC_CH5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH5">AT91C_ADC_CH5</a></font></td><td><b>Channel 5</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_CH6"></a><b>ADC_CH6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH6">AT91C_ADC_CH6</a></font></td><td><b>Channel 6</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_CH7"></a><b>ADC_CH7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_CH7">AT91C_ADC_CH7</a></font></td><td><b>Channel 7</b></td></tr>
</null></table>
<a name="ADC_SR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_SR  <i>ADC Status Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_SR">AT91C_ADC_SR</a></i> 0xFFFD801C</font></null></ul><br>EOCx:<br>0 = Channel x is disabled, or the conversion is not finished.<br>1 = Channel x is enabled and conversion is complete.<br>OVREx:<br>0 = No overrun on the channel x since the last read of ADC_SR.<br> 1 = There has been an overrun on the channel x since the last read of ADC_SR.<br>DRDY:<br>0 = No data has been converted since the last read of ADC_LCDR.<br> 1 = At least one data has been converted since the last read of ADC_LCDR.<br>GOVRE:<br>0 = No Overrun Error occured since the last read of ADC_LCDR.<br> 1 = At least one Overrun Error has occured since the last read of ADC_LCDR.<br>ENDBUF:<br>0 = The PDC does not report an end of buffer.<br> 1 = The PDC reports an end of buffer.<br>BUFFULL:<br>0 = The PDC does not report a buffer full.<br> 1 = The PDC reports a buffer full.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_EOC0"></a><b>ADC_EOC0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC0">AT91C_ADC_EOC0</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_EOC1"></a><b>ADC_EOC1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC1">AT91C_ADC_EOC1</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_EOC2"></a><b>ADC_EOC2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC2">AT91C_ADC_EOC2</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_EOC3"></a><b>ADC_EOC3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC3">AT91C_ADC_EOC3</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_EOC4"></a><b>ADC_EOC4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC4">AT91C_ADC_EOC4</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_EOC5"></a><b>ADC_EOC5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC5">AT91C_ADC_EOC5</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_EOC6"></a><b>ADC_EOC6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC6">AT91C_ADC_EOC6</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_EOC7"></a><b>ADC_EOC7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC7">AT91C_ADC_EOC7</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="ADC_OVRE0"></a><b>ADC_OVRE0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE0">AT91C_ADC_OVRE0</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="ADC_OVRE1"></a><b>ADC_OVRE1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE1">AT91C_ADC_OVRE1</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="ADC_OVRE2"></a><b>ADC_OVRE2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE2">AT91C_ADC_OVRE2</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="ADC_OVRE3"></a><b>ADC_OVRE3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE3">AT91C_ADC_OVRE3</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="ADC_OVRE4"></a><b>ADC_OVRE4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE4">AT91C_ADC_OVRE4</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="ADC_OVRE5"></a><b>ADC_OVRE5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE5">AT91C_ADC_OVRE5</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14</td><td align="CENTER"><a name="ADC_OVRE6"></a><b>ADC_OVRE6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE6">AT91C_ADC_OVRE6</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="ADC_OVRE7"></a><b>ADC_OVRE7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE7">AT91C_ADC_OVRE7</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="ADC_DRDY"></a><b>ADC_DRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DRDY">AT91C_ADC_DRDY</a></font></td><td><b>Data Ready</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="ADC_GOVRE"></a><b>ADC_GOVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_GOVRE">AT91C_ADC_GOVRE</a></font></td><td><b>General Overrun</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="ADC_ENDRX"></a><b>ADC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_ENDRX">AT91C_ADC_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="ADC_RXBUFF"></a><b>ADC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_RXBUFF">AT91C_ADC_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
</null></table>
<a name="ADC_LCDR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_LCDR  <i>ADC Last Converted Data Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_LCDR">AT91C_ADC_LCDR</a></i> 0xFFFD8020</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_LDATA"></a><b>ADC_LDATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_LDATA">AT91C_ADC_LDATA</a></font></td><td><b>Last Data Converted</b><br>Data converted is placed at the end of conversion and remains until a new one is completed.</td></tr>
</null></table>
<a name="ADC_IER"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_IER  <i>ADC Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_IER">AT91C_ADC_IER</a></i> 0xFFFD8024</font></null></ul><br>0 = No effect. 1 = Enables the corresponding interrupt.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_EOC0"></a><b>ADC_EOC0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC0">AT91C_ADC_EOC0</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_EOC1"></a><b>ADC_EOC1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC1">AT91C_ADC_EOC1</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_EOC2"></a><b>ADC_EOC2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC2">AT91C_ADC_EOC2</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_EOC3"></a><b>ADC_EOC3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC3">AT91C_ADC_EOC3</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_EOC4"></a><b>ADC_EOC4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC4">AT91C_ADC_EOC4</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_EOC5"></a><b>ADC_EOC5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC5">AT91C_ADC_EOC5</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_EOC6"></a><b>ADC_EOC6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC6">AT91C_ADC_EOC6</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_EOC7"></a><b>ADC_EOC7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC7">AT91C_ADC_EOC7</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="ADC_OVRE0"></a><b>ADC_OVRE0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE0">AT91C_ADC_OVRE0</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="ADC_OVRE1"></a><b>ADC_OVRE1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE1">AT91C_ADC_OVRE1</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="ADC_OVRE2"></a><b>ADC_OVRE2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE2">AT91C_ADC_OVRE2</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="ADC_OVRE3"></a><b>ADC_OVRE3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE3">AT91C_ADC_OVRE3</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="ADC_OVRE4"></a><b>ADC_OVRE4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE4">AT91C_ADC_OVRE4</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="ADC_OVRE5"></a><b>ADC_OVRE5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE5">AT91C_ADC_OVRE5</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14</td><td align="CENTER"><a name="ADC_OVRE6"></a><b>ADC_OVRE6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE6">AT91C_ADC_OVRE6</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="ADC_OVRE7"></a><b>ADC_OVRE7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE7">AT91C_ADC_OVRE7</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="ADC_DRDY"></a><b>ADC_DRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DRDY">AT91C_ADC_DRDY</a></font></td><td><b>Data Ready</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="ADC_GOVRE"></a><b>ADC_GOVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_GOVRE">AT91C_ADC_GOVRE</a></font></td><td><b>General Overrun</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="ADC_ENDRX"></a><b>ADC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_ENDRX">AT91C_ADC_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="ADC_RXBUFF"></a><b>ADC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_RXBUFF">AT91C_ADC_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
</null></table>
<a name="ADC_IDR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_IDR  <i>ADC Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_IDR">AT91C_ADC_IDR</a></i> 0xFFFD8028</font></null></ul><br>0 = No effect. 1 = disables the corresponding interrupt.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_EOC0"></a><b>ADC_EOC0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC0">AT91C_ADC_EOC0</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_EOC1"></a><b>ADC_EOC1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC1">AT91C_ADC_EOC1</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_EOC2"></a><b>ADC_EOC2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC2">AT91C_ADC_EOC2</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_EOC3"></a><b>ADC_EOC3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC3">AT91C_ADC_EOC3</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_EOC4"></a><b>ADC_EOC4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC4">AT91C_ADC_EOC4</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_EOC5"></a><b>ADC_EOC5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC5">AT91C_ADC_EOC5</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_EOC6"></a><b>ADC_EOC6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC6">AT91C_ADC_EOC6</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_EOC7"></a><b>ADC_EOC7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC7">AT91C_ADC_EOC7</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="ADC_OVRE0"></a><b>ADC_OVRE0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE0">AT91C_ADC_OVRE0</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="ADC_OVRE1"></a><b>ADC_OVRE1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE1">AT91C_ADC_OVRE1</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="ADC_OVRE2"></a><b>ADC_OVRE2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE2">AT91C_ADC_OVRE2</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="ADC_OVRE3"></a><b>ADC_OVRE3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE3">AT91C_ADC_OVRE3</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="ADC_OVRE4"></a><b>ADC_OVRE4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE4">AT91C_ADC_OVRE4</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="ADC_OVRE5"></a><b>ADC_OVRE5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE5">AT91C_ADC_OVRE5</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14</td><td align="CENTER"><a name="ADC_OVRE6"></a><b>ADC_OVRE6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE6">AT91C_ADC_OVRE6</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="ADC_OVRE7"></a><b>ADC_OVRE7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE7">AT91C_ADC_OVRE7</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="ADC_DRDY"></a><b>ADC_DRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DRDY">AT91C_ADC_DRDY</a></font></td><td><b>Data Ready</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="ADC_GOVRE"></a><b>ADC_GOVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_GOVRE">AT91C_ADC_GOVRE</a></font></td><td><b>General Overrun</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="ADC_ENDRX"></a><b>ADC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_ENDRX">AT91C_ADC_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="ADC_RXBUFF"></a><b>ADC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_RXBUFF">AT91C_ADC_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
</null></table>
<a name="ADC_IMR"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_IMR  <i>ADC Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_IMR">AT91C_ADC_IMR</a></i> 0xFFFD802C</font></null></ul><br>0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ADC_EOC0"></a><b>ADC_EOC0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC0">AT91C_ADC_EOC0</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ADC_EOC1"></a><b>ADC_EOC1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC1">AT91C_ADC_EOC1</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ADC_EOC2"></a><b>ADC_EOC2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC2">AT91C_ADC_EOC2</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="ADC_EOC3"></a><b>ADC_EOC3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC3">AT91C_ADC_EOC3</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="ADC_EOC4"></a><b>ADC_EOC4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC4">AT91C_ADC_EOC4</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="ADC_EOC5"></a><b>ADC_EOC5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC5">AT91C_ADC_EOC5</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="ADC_EOC6"></a><b>ADC_EOC6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC6">AT91C_ADC_EOC6</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="ADC_EOC7"></a><b>ADC_EOC7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_EOC7">AT91C_ADC_EOC7</a></font></td><td><b>End of Conversion</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="ADC_OVRE0"></a><b>ADC_OVRE0</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE0">AT91C_ADC_OVRE0</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="ADC_OVRE1"></a><b>ADC_OVRE1</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE1">AT91C_ADC_OVRE1</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="ADC_OVRE2"></a><b>ADC_OVRE2</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE2">AT91C_ADC_OVRE2</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="ADC_OVRE3"></a><b>ADC_OVRE3</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE3">AT91C_ADC_OVRE3</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="ADC_OVRE4"></a><b>ADC_OVRE4</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE4">AT91C_ADC_OVRE4</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="ADC_OVRE5"></a><b>ADC_OVRE5</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE5">AT91C_ADC_OVRE5</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14</td><td align="CENTER"><a name="ADC_OVRE6"></a><b>ADC_OVRE6</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE6">AT91C_ADC_OVRE6</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="ADC_OVRE7"></a><b>ADC_OVRE7</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_OVRE7">AT91C_ADC_OVRE7</a></font></td><td><b>Overrun Error</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="ADC_DRDY"></a><b>ADC_DRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DRDY">AT91C_ADC_DRDY</a></font></td><td><b>Data Ready</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="ADC_GOVRE"></a><b>ADC_GOVRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_GOVRE">AT91C_ADC_GOVRE</a></font></td><td><b>General Overrun</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="ADC_ENDRX"></a><b>ADC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_ENDRX">AT91C_ADC_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="ADC_RXBUFF"></a><b>ADC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_RXBUFF">AT91C_ADC_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
</null></table>
<a name="ADC_CDR0"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR0  <i>ADC Channel Data Register 0</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR0">AT91C_ADC_CDR0</a></i> 0xFFFD8030</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR1"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR1  <i>ADC Channel Data Register 1</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR1">AT91C_ADC_CDR1</a></i> 0xFFFD8034</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR2"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR2  <i>ADC Channel Data Register 2</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR2">AT91C_ADC_CDR2</a></i> 0xFFFD8038</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR3"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR3  <i>ADC Channel Data Register 3</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR3">AT91C_ADC_CDR3</a></i> 0xFFFD803C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
</null></table>
<a name="ADC_CDR4"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR4  <i>ADC Channel Data Register 4</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR4">AT91C_ADC_CDR4</a></i> 0xFFFD8040</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
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<a name="ADC_CDR5"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR5  <i>ADC Channel Data Register 5</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR5">AT91C_ADC_CDR5</a></i> 0xFFFD8044</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
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<a name="ADC_CDR6"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR6  <i>ADC Channel Data Register 6</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR6">AT91C_ADC_CDR6</a></i> 0xFFFD8048</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
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<a name="ADC_CDR7"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> ADC_CDR7  <i>ADC Channel Data Register 7</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="AT91SAM7S256_h.html#AT91C_ADC_CDR7">AT91C_ADC_CDR7</a></i> 0xFFFD804C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="ADC_DATA"></a><b>ADC_DATA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_ADC_DATA">AT91C_ADC_DATA</a></font></td><td><b>Converted Data</b><br>The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.<br> The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.</td></tr>
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<a name="ADC_PDC"></a><h4><a href="#ADC">ADC</a>: <i><a href="AT91SAM7S256_h.html#AT91S_PDC">AT91S_PDC</a></i> ADC_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>ADC</b> <i><a href="#AT91C_ADC_ADC">AT91C_ADC_ADC</a></i> 0xFFFD8100</font></null></ul></null><hr></html>
